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publication release date: april 2000 - 1 - revision a6 general description the w536xxxt, a member of viewtalk tm family, is a high-performance 4-bit micro-controller (uc) with built-in speech unit, melody unit and 64seg * 32 com lcd driver unit which includes internal regulator,pump circuit and dedicated two pages lcd ram. the 4-bit uc core contains dual clock source, 4-bit alu, two 8-bit timers, one 14 bits divider, maximum 24 pads for input or output, 8 interrupt sources and 8-level nesting for subroutine/interrupt applications. speech unit, integrated as a single chip with maximum 128 seconds (based on 6.4k sample rate with 5 bits mdpcm) , is capable of expanding to 512 seconds speech addressed by external memory w55xxx with serial bus interface. it can be implemented with winbond power speech using mdpcm algorithm. melody unit provides dual tone output and can store up to 1k notes. power reduction mode is also built in to minimize power dissipation. it is ideal for games, educational toys, remote controllers, watches, clocks and other application products which incorporate both lcd display and speech. body w536030t w536060t w536090t W536120T voice 30 sec 60 sec 90 sec 120 sec i/o pad 4i/o,4i (ra/rd) 4i/o, 8i (ra/rc/rd) 8i/o, 8i , 8o (ra/rb/rc/rd/re/rf) 8i/o, 8i, 8o (ra/rb/rc/rd/re/rf) wdt disable/enable (mask option) y y y y sub-clock rc/xtal mode (mask option) y y y y rd port shared as serial bus (mask option) y(1) y(1) n n (2) tri-state serial bus (mask option) ( 3) y y y y cascaded voice rom through serial bus (2) y(1) y(1) n y (1) share 3 pads of rd port (rd1/rdp, rd2/spdata and rd3/wrp) (2) dedicate serial bus 3 pads (rdp, spdata and wrp) to interface with w55xxx. cascaded voice rom can help user to expand voice up to 512 sec by w55xxx chip. (3) tri-state serial bus mask option can float serial bus while voice playing is no active. let this mask option is disabled to get minimum power consumption in general. features ? operating voltage: 2.4 volt ~ 5.5 volt ? watch dog disabled/enabled by mask option ? dual clock operating system ? main clock with rc/crystal (400 khz to 4 mhz) ? sub-clock with 32.768 khz rc/crystal by mask option

publication release date:april 2000 - 2 - revision a6 ? memory ? program rom (p-rom): 64k 20 (rom bank0, 1, 2, 3, 4, 5, 6) ? data ram (w-ram): 1.4k 4 bit (ram bank 0 is 896 nibbles from 0:000~0:37f and 0:380~0:3ff are mapped to special register. ram bank f is 512 nibbles from f:200~f:3ff either data ram or dedicated to script kernel ) ? lcd ram (l-ram): 512 4 bit 2 pages (ram bank1, 2 from 200~3ff) ? maximum 24 input/output pads ? ports for input only: 8 pads (rc, rd port; rd1~3 can share as serial bus for external memory w55xxx interface @w536030t/060t) ? ports for output only: 8 pads (re & rf port; w536090t/120t available only) ? ports for input/output: 8 pads (ra and rb port; rb port is available for w536090t/W536120T only) ? power-down mode ? hold mode (except for 32khz oscillator) ? stop mode (including 32khz oscillator and release by rd or rc port) ? eight types of interrupts ? five internal interrupts (divider, timer 0, timer 1, speech, melody ) ? three external interrupts (port rc, rd, ra) ? one built-in 14-bit clock frequency divider circuit ? two built-in 8-bit programmable countdown timers ? timer 0: one of two clock sources (fosc/4 or fosc/1024) can be selected ? timer 1: built-in auto-reload function includes internal timer, external event counter from rc.0 ? built-in 18/14-bit watchdog timer for system reset. ? powerful instruction sets ? 8-level subroutine (including interrupt) nesting ? lcd driver unit capability ? vlcd higher than (vdd-0.5v) ? built-in voltage regulator to v2 pad ? 64 seg 32 com ? 1/32 or 1/16 duty, 1/5 or 1/4 bias, internal pump circuit option by special register ? com24~ 31 and seg40~63 can be shared as general input/output by special register ? either uc rom or voice rom used as lcd picture ? speech function ? provided 1m / 2m/ 3m/ 4m bits voice rom for w536030t/060t/090t/120t based on 5 bits mdpcm algorithm ? voice rom (v-rom) available for uc data or lcd picture data. ? maximum 8*256 label/interrupt vector (voice section number) available ? provide two types of speech busy flag to either each go or each trigger ? maximum up to 16m bits speech address capability interface with external memory w55 xxx through serial bus. ? melody function ? provide 1k notes (22bits/note) dedicated melody rom ? provide two types of melody busy flag to uc either each note or each song ? provide 6 kinds of beat, 16 kinds of tempo, and pitch range from g3# to c7 ? tremolo, triple frequency and 3 kinds of percussion available ? maximum 31 songs available ? can mix speech with melody ? multi-engine controller ? direct driving speaker/buzzer or dac output ? chip on board available

publication release date:april 2000 - 3 - revision a6 block diagram xin xout x32i x32o lcd driver pc stack (8 levels) timer 0 timing generator seg0~63 v3,v4,v5,v6 timer 1 watch dog alu acc divide rom 64k*20bit dh1,dh2 com0~31 ram 1.4k*4bit special register hcf hef ief evf flag1 psr0 mr0 pef flag0 lpx3 pm0 lpx2 lpx0 lpx1 port ra vlcd pump & regulator tone ra0~3 res lpx4 port rc port rd rc0~3 rd0~3 lpx5 lpy0 lpy1 spc mld dual tone melody (1k notes) mld_play mld_busy speech mdpcm core spc_play spc_busy pwm1/dac rosc parallel to serial interrupt ,hold & stop control re0~3 rf0~3 port rb rb0~3 port re port rf wrp rdp spdata v2 vdda vdd vss vssp test voice rom (1m /2m/3m/4m bits) pwm/dac mix block pwm2 vddp lpxy vssa shared_rom data

publication release date:april 2000 - 4 - revision a6 pad description symbol i/o function xin/rxin i input pad for main clock oscillator. it can be connected to crystal when crystal mode is selected (scr0.2=1), otherwise connect a resistor to vdd to generate main system clock while rc mode is selected (scr0.2=0 and default). oscillator can be enabled or stopped by set scr0.1 to 1 or clear to 0 separately. external capacitor connects to start oscillation while crystal mode xout o output pad for oscillator which is connected to another crystal pad when in crystal mode. external capacitor connects to start oscillation when in crystal mode. x32i/rsub1 i 32.768 khz crystal input pad or external resistor node 1 by mask option . external 15~20pf capacitor connects to get more accurate clock when in crystal mode. x32o/rsub2 o 32.768 khz crystal output pad or external resistor node 2 by mask option. external 15~20pf capacitor connects to get more accurate clock when in crystal mode. ra0 ~ ra3/tone i/o general input/output port specified by pm1 register. if output mode is selected, pm0 register bit 0 can be used to specify cmos/nmos driving capability option. initial state is input mode. ra3 may be uses as tone if bit 0 of mr0 special register is set to logic 1. an interrupt source. rb0 ~ rb3 i/o general input/output port specified by pm2 register. if output mode is selected, pm0 register bit 1 can be used to specify cmos/nmos driving capability option. initial state is input mode (w536090t /W536120T only.) rc0 ~ rc3 i 4-bit schmitter input with internal pull high option specified by pm3 register bit 2. each pad has an independent interrupt capability specified by pefl special register. interrupt and stop mode wake up source. rc0 is also the external event counter source of timer1. (w536060t/090t/120t only.) rd0 rd1/rdp rd2/spdata rd3/wrp (4) i 4-bit schmitter input port with internal pull high option specified by pm3 register bit 3. each pad has an independent interrupt capability specified by pefh special register. interrupt and stop mode wake up source. rd1~3 will be shared as the external memory w55xxx interface pads while rd port shared as serial bus mask option is enabled @w536030t/060t. re0~re3 o output port only. pm3 register bit 0 can be used to specify cmos/nmos driving capability option. (w536090t/120t only) rf0~rf3 o output port only. pm3 register bit 1 can be used to specify cmos/nmos driving capability option. (w536090t/120t only) res i system reset pad, active low with internal pull-high resistor. test i test pad. active high with internal pull low resistor.

publication release date:april 2000 - 5 - revision a6 rosc i connect resistor to vdd pad to generate speech or melody playing clock source. pwm1/dac o while speech or melody is active , pwm1/dac is speaker direct driving output or dac output controlled by voice output file. pwm2 o while speech or melody is active, pwm2 is another speaker direct driving output. wrp (5) o external serial memory address write clock for voice extension (W536120T only). the "tri-sate serial bus" mask option can use tri-sate wrp pad while external voice rom is not available. default that mask option is disabled and fixes wrp pad state while external voice is not enabled to get chip low power consumption. rdp (5) o external serial memory address read clock for voice extension. (W536120T only).the pad state is same as wrp pad depended on "tri-sate serial bus" mask option. spdata (5) i/o external serial memory data in/out for voice extension (W536120T only).the pad state is same as wrp pad depended on "tri-sate serial bus" mask option. seg0 ? seg39 o dedicated lcd segment output pads. seg40/portn.0 ? seg43/portn.3 o/o lcd segment output pads, and can be shared as general output by register lcdm3 bit 1. default function is segment pad. seg44/portm.0 ? seg47/portm.3 o/i lcd segment output pads, and can be shared as general input by register lcdm3 bit 0. default function is segment pad and pm5.1=0 to inhibit lcd waveform abnormal. seg48/portl.0 ? seg51/portl.3 o/o lcd segment output pads, and can be shared as general output by register lcdm2 bit 0. default function is segment pad. seg52/portk.0 ? seg55/portk.3 o/i lcd segment output pads, and can be shared as general input by register lcdm2 bit 1. default function is segment pad and pm5.0=0 to inhibit lcd waveform abnormal. seg56/portj.0 ? seg59/portj.3 o/io lcd segment output pads, and can be shared as general input/output by register lcdm2 bit 2. pm4 register is used to select input or output while shared i/o function is active. default function is segment pad and pm4.3=0 to inhibit lcd waveform abnormal. seg60/porti.0 ? seg63/porti.3 o/io lcd segment output pads, and can be shared as general input/output by register lcdm2 bit 3. pm4 register is used to select input or output while shared i/o function is active. default function is segment pad and pm4.2=0 to inhibit lcd waveform abnormal.

publication release date:april 2000 - 6 - revision a6 com0 ? com15 o lcd common signal output pads either 1/32 duty or 1/16 duty. the lcd frame rate is controlled by lcdm1 register, and default value lcdm1=0111b with 64hz frame rate. com16 ? com23 o lcd common signal output pads while 1/32 duty is active. the lcd frame rate is controlled by lcdm1 register, and default value lcdm1=0111b with 64hz frame rate. com24/portp.0 ? com27/portp.3 o/o lcd common signal output pads, or shared as general output by register lcdm3.2 when in 1/16 duty mode. default function is common function. com28/porto.0 ? com31/porto.3 o/i lcd common signal output pads, or shared as general input by register lcdm3.2 when in 1/16 duty mode. default function is common function and pm5.2=0 to inhibit lcd waveform abnormal. dh1, dh2 (6) o connection terminal for voltage double capacitor with 0.1uf. the dh2 connects to capacitor positive node and dh1 negative node if polar capacitor is used. v3 ~ v6 (6) o lcd com/seg output driving voltage. need an external 0.1uf capacitor to every pad terminal. v2 (6) i/o voltage regulator output pad. an external capacitor is a must. output level can be controlled from 0~fh by lcdm4 register. if internal pump is enabled (lcdm3.3=0 and default value), lcd operating voltage (vlcd) will be 4*v2 or 5*v2 depending on 1/4 bias or 1/5 bias. a limitation should be noted that vlcd must be higher than (vdd-0.5v) to avoid chip leakage current. while external reference voltage is selected (lcdm3.3=1), v2 pad input voltage can not be over 1.5 volt to inhibit chip damage . vssp i power ground for pwm or dac playing output. vssa(7) i power ground. vss i power ground vddp i power source for pwm or dac playing output. vdda(7) i power ground. vdd i power ground. (4) rd1~3 are shared as rdp/spdata/wrp to interface with w55xxx @w536030t/060t (5) @W536120T only (6) 0.1uf is default value, and capacitor value should be larger than 0.1uf if lcd dot size over 0.5mm*0.5mm. (7) external application circuit should connect together, please refer to application circuit. to sure chip operation properly, please bond all vddp,vdda, vdd,vssp,vss and vssa pads and connect vssp, vss from chip outside pcb circuit. vssa and vdda are for W536120T only

publication release date:april 2000 - 7 - revision a6 absolute maximum ratings parameter rating unit supply voltage to ground potential -0.3 to +7.0 v applied input/output voltage -0.3 to +7.0 v power dissipation 120 mw ambient operating temperature 0 to +70 c storage temperature -55 to +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc characteristics (vdd ? vss = 3.0v, f m = 4 mhz with rc mode, fs = 32.768 khz, with xtal mode, t a = 25 c, stn lcd panel on with dot size 0.5mm*0.5mm; unless otherwise specified) parameter sym. conditions min typ max unit op. voltage v dd 2.4 5.5 v op. current i op1 dual clock with crystal - 600 700 ua (no load, no voice, dual clock with rc type 600 700 no melody) sub-clock only, lcd off 40 50 sub-clock only, lcd on 70 90 hold mode current (no load, lcd off) i op2 sub-clock active only 6 10 ua hold mode current (no load, lcd on) i op3 sub-clock active only 70 ua stop mode current i op4 lcd auto off 1 ua rdp/wrp output high current io h1 vout=2.7v -0.8 ma rdp/wrp output low current io l1 vout=0.4v 0.8 ma input low voltage v il - vss - 0.3 vdd input high voltage v ih - 0.7 - 1 vdd port ra, rb output low voltage v abl iol = 2.0 ma - - 0.4 v port ra, rb output high voltage v abh ioh = -2.0 ma 2.4 - - v pull-up resistor r cd port rc, rd 200 300 400 k ? res pull-up resistor r res - 50 100 200 k ? pwm1/2 source current (8) i sph volume option =00 -20 ma (r load =8 ? between pwm1 volume option =01 -70 and pwm2 ) volume option =10 -110 volume option =11 -135 pwm1/2 sink current (8) i spl volume option =00 20 ma (r load =8 ? between pwm1 volume option =01 70 and pwm2 ) volume option =10 110 volume option =11 135

publication release date:april 2000 - 8 - revision a6 dac output current i dac vdd=3v, rl=100ohm -4 -5 -6 ma lcd supply current i lcd no load, all seg. on - 50 - a com/seg on resistor r on ioh = 50 a 5k 10k ? v2 pad output voltage v rr depended on lcdm4 0.7 1.45 v v2 pad output deviation (9) v d1 no load 5 % v2 pad voltage step v r2 lcdm4 increased 1 50 mv v6 pad output voltage (lcd's vlcd depended on v lcd 1/4 bias & no load 3.8 * v2 3.85 * v2 3.9 * v2 v lcdm4 register ) (9) 1/5 bias & no load 4.75 * v2 4.8 * v2 4.85 * v2 v2 input voltage v ext lcdm3.3=1 1.5 v (8) pwm current deviation will be 20%. (9) vlcd deviation is governed by lcd dot size. more larger lcd dot will get larger deviation. ac charateristics (vdd ? vss = 3.0v, f m = 4 mhz with rc mode, fs = 32.768 khz, with xtal mode, t a = 25 c, stn lcd on with dot size 0.5mm*0.5mm; unless otherwise specified) parameter sym. conditions min. typ. max. unit sub-clock frequency f sub crystal type and x32in and x32o with 17pf external cap. 32768 hz main-clock frequency f m rc type/crystal type 400k - 4m hz chip operation frequency f osc scr0.0=1,f sys =f sub 32768 hz scr0.0=0;f sys = f main 400k - 4m instruction cycle time t cyc one machine cycle - 4/f osc - s reset active width t raw fosc = 32.768 khz 1 - - s interrupt active width t iaw fosc = 32.768 khz 1 - - s main clock rc frequency f rxin rxin =680k ? 1m hz (10) rxin =330k ? 2m rxin =200k ? 3m rxin =130k ? 4m sub-clock ring oscillator f rsub r sub =680k ? 32 khz sub-clock oscillation stable time @ cold start f stop r sub =680k ? 0.8 1 s frequency deviation of main-clock f rxin 2mhz ? f f f(3v) f(2.4v) f(3v) ? 10 % frequency deviation of main-clock f rxin = 3mhz ? f f f(3v) f(2.4v) f(3v) ? 15 % frequency deviation of main-clock f rxin =4 mhz ? f f f(3v) f(2.4v) f(3v) ? 20 % rosc frequency f rosc r osc =680k ? 3 mhz frequency deviation of f rosc = 3mhz ? f f f(3v) f(2.4v) f(3v) ? 7.5 % frame frequency f lcd lcdm1=0111 b(default) 64 hz (10) the deviation will be +20% while vdd drops from 5.5v to 2.4v based on same resistor

publication release date:april 2000 - 9 - revision a6 iop vs. main clock rc mode 0 200 400 600 800 1000 1234 freq (mhz) iop (ua) 3v 4. 5v oscillation freq vs. sub-clock 20 24 28 32 36 40 44 560 620 680 750 820 1k rsub (kohm) fsub (khz) 3v 4. 5v

publication release date:april 2000 - 10 - revision a6 main freq vs. rxin 0 1 2 3 4 5 6 130 150 160 200 330 680 2k 3k rxin (kohm) fmain (mhz) 2.4v 3v 4.5v 5.5v voice operating freq. vs. rosc 2 2. 5 3 3. 5 4 4. 5 470 560 680 910 rosc (kohm) freq (mhz) 3v 4. 5v

publication release date:april 2000 - 11 - revision a6 application circuit--1: sub clock with rc mode vlcd> (vdd-0.5v) panel w536xxxt rc0~3 rd0~3 ra0~3 rb0~3 re0~3 x32in x32o battery r4 c10 vddp r1 r3 rosc xin res c9 vddp com0~31 seg0~63 pwmn pwmp/dac rf0~3 ( * 2) r5 c4 v4 c6 v6 c5 v5 c2 v2 c3 v3 c1 dh2 dh1 470 (*3) (*1) vdd c11 r2 vssp vssa vss vdd vdda +- component c1~c6 c7,c8 c9,c10 c11 r1 r2 r3 r4 value 0.1uf - 0.1uf 1uf 680k 680k 680kohm/1mhz 330kohm/2mhz 200kohm/3mhz 130kohm/4mhz 100 note: (1) c1~c6 depends on lcd panel dot size. (2) option r5 equals to 100 ? if high noise immunity is needed. (3) for dac option application. (4) to sure chip operation properly, please bond all vddp, vdda,vdd, vssp,vss and vssa pads. vssa and vdda are for w536090t/120t only

publication release date:april 2000 - 12 - revision a6 application circuit--- 2 : sub clock with crystal mode vlcd> (vdd-0.5v) panel w536xxxt rc0~3 rd0~3 ra0~3 rb0~3 re0~3 battery r4 c10 vddp r1 r3 rosc xin res c9 vddp com0~31 seg0~63 pwmn pwmp/dac rf0~3 ( * 2) r5 c4 v4 c6 v6 c5 v5 c2 v2 c3 v3 c1 dh2 dh1 470 (*3) (*1) vdd c11 vssp vssa vss vdd vdda 32.768khz c7 x32in x32o c8 +- component c1~c6 c7,c8 c9,c10 c11 r1 r2 r3 r4 value 0.1uf 15~20pf 0.1uf 1uf 680k - 680kohm/1mhz 330kohm/2mhz 200kohm/3mhz 130kohm/4mhz 100 note: (1) c1~c6 depends on lcd panel dot size. (2) option r5 equals to 100 ? if high noise immunity is needed. (3) for dac option application. (4) to sure chip operation properly, please bond all vddp, vdda,vdd, vssp,vss and vssa pads. vssa and vdda are for w536090t/120t only

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